1. Field of the Invention
The present invention relates to a push-pull amplifier that is provided in an IC or the like that is formed through a CMOS process.
2. Description of the Related Art
FIG. 1 shows a conventional single-input, single-output push-pull amplifier, which may be used as the output stage of an operational amplifier. In such a case, it is desirable that the output of a differential amplifier utilizing n-channel transistors as its inputs be used as the input of the push-pull amplifier.
The push-pull amplifier includes p-channel MOSFETs 21 and 25 (which will be referred to simply as pMOSes 21 and 25 hereinafter); n-channel MOSFETs 22, 23, 24, and 26 (which will be referred to simply as nMOSes 22, 23, 24, and 26 hereinafter); a constant-current source 27; a phase compensation capacitor 28; an input terminal IN for receiving an input signal Vin; and an output terminal OUT for outputting an output signal. The input signal Vin is directly supplied to the pMOSes 21 and 25 and to the nMOS 23. The pMOS 25 and nMOS 26 constitute a push-pull circuit (the output stage).
The pMOS 21 has its gate, source and drain electrodes connected to the input terminal IN, a power supply line VDD and a node ND21, respectively. The gate electrode, source electrode and drain electrode will be referred to simply as gate, source and drain, respectively, hereinafter. The nMOS 22 has its gate and drain both connected to the node ND21 and has its source connected to a ground line VSS. The nMOS 23 has its gate, source and drain connected to the input terminal IN, a node ND22 and a node ND23, respectively. The nMOS 24 has its gate, source and drain connected to the node ND21, the ground line VSS and the node ND22, respectively. The pMOS 25 has its gate, source and drain connected to the input terminal IN, the power supply line VDD and the output terminal OUT, respectively. The nMOS 26 has its gate, source and drain connected to the node ND22, the ground line VSS and the output terminal OUT, respectively. The current source 27 supplies a constant current 127 to the node ND23. The capacitor 28 is inserted between the input terminal IN and the output terminal OUT.
In the output stage of the push-pull amplifier shown in FIG. 1, the gate of the pMOS 25 directly receives the input signal Vin. Thus, the voltage gain of the gate voltage of the pMOS 25 to the input signal Vin is xe2x80x9c1xe2x80x9d. Meanwhile, the gate of the nMOS 26 receives the input signal Vin via the pMOS 21, nMOS 23 and current mirror circuit (the nMOSes 22 and 24). Thus, the voltage gain of the gate voltage of the nMOS 26 to the input signal Vin is not equal to the voltage gain of the gate voltage of the pMOS 25.
The voltage gain dVn/dVin of the gate voltage of the nMOS 26 to the input signal Vin will be obtained below. It is now assumed here that the transfer conductance and drain-to-source resistance of the pMOS 21 are gm2, and Rds21, respectively; the transfer conductance and drain-to-source resistance of the nMOS 22 are gm22 and Rds22, respectively; the transfer conductance and drain-to-source resistance of the nMOS 23 are gm23 and Rds23, respectively; and that the transfer conductance and drain-to-source resistance of the nMOS 24 are gm24 and Rds24, respectively. It is also assumed here that the voltage between the drain of the nMOS 23 and the ground (the voltage at the node ND22) is V23; the gate-to-source voltage of the nMOS 24 is Vx; the gate-to-source voltage of the nMOS 26 is Vn; and that the internal resistance of the constant-current source 27 is Rds27.
The above parameters establish the following equations (1), (2), and (3).                                           gm21            ⁡                          (                              VDD                -                Vin                            )                                +                                    VDD              -              Vx                        Rds21                          =                              gm22            *            Vx                    +                      Vx            Rds22                                              (        1        )                                          I27          +                                    VDD              -              V23                        Rds27                          =                              gm23            ⁡                          (                              Vin                -                Vn                            )                                +                                    V23              -              Vn                        Rds23                                              (        2        )                                          I27          +                                    VDD              -              V23                        Rds27                          =                              gm24            ·            Vx                    +                      Vn            Rds24                                              (        3        )            
From the above equations (1) through (3), the voltage gain dVn/dVin of the gate voltage Vn of the nMOS 26 to the input signal Vin can be expressed by the following equation (4).                                                                                           ⅆ                  Vn                                                  ⅆ                  Vin                                            =                              xe2x80x83                            ⁢                                                gm23                  -                                      2                    ⁢                                          gm24                      ·                                                                        -                          gm21                                                                                                      1                            Rds21                                                    +                                                      1                            Rds22                                                    +                          gm22                                                                                                                                                          1                    Rds23                                    +                                      2                    Rds24                                    +                  gm23                                                                                                        =                              xe2x80x83                            ⁢                                                                                          gm23                      ⁡                                              (                                                  Rds21                          +                          Rds22                          +                                                      gm22                            ·                            Rds21                            ·                            Rds22                                                                          )                                                              ⁢                                          Rds23                      ·                      Rds24                                                        +                                      2                    ⁢                                          gm21                      ·                      gm24                      ·                      Rds21                      ·                      Rds22                      ·                      Rds23                      ·                      Rds24                                                                                                            (                                          Rds21                      +                      Rds22                      +                                              gm22                        ·                        Rds21                        ·                        Rds22                                                              )                                    ⁢                                      (                                          Rds24                      +                                              2                        ⁢                        Rds23                                            +                                              gm23                        ·                        Rds23                        ·                        Rds24                                                              )                                                                                                          (        4        )            
Since gmxc2x7Rds is, in general, much greater than 1 (i.e., gm-Rds greater than  greater than 1), the following equation (5) can be figured out by approximating the equation (4).                                           ⅆ            Vn                                ⅆ            Vin                          =                              2            ⁢                                          gm21                ·                gm24                                            gm22                ·                gm23                                              +          1                                    (        5        )            
Moreover, when gm22 and gm24 of the nMOSes 22 and 24, respectively, constituting the current mirror circuit are equal to each other, the voltage gain dVn/dVin can be obtained by the following equation (6).                                           ⅆ            Vn                                ⅆ            Vin                          =                              2            ⁢                          gm21              gm23                                +          1                                    (        6        )            
There may be a case when the gate voltage Vn of the nMOS 26 in the output stage has a value that is slightly greater than the threshold voltage of the nMOS 26. In such a case, it is necessary to adjust various values so that the voltage difference (Vinxe2x88x92Vn) between the voltage of the input signal (Vin) and the gate voltage of the nMOS 26 (Vn), that is, the gate-to-source voltage of the nMOS 23, can be large. Thus, it is necessary to make adjustments so that the threshold voltage of the nMOS 23 is higher, or so that the gain coefficient xcex2 of the nMOS 23 is smaller, by elongating the gate length of the nMOS 23, for example. As a result of this, gm23 becomes smaller. As shown in the equation (6), when gm23 becomes smaller, the voltage gain dVn/dVin becomes larger.
Therefore, in the push-pull amplifier shown in FIG. 1, the difference between the gain at the pMOS 25 (=1) and the gain at the nMOS 26 (=2xc2x7(gm21/gm23)+1, as shown in the equation (6)) in the output stage with respect to the input signal disadvantageously becomes larger. Consequently, since the gain varies between when the pMOS 25 mainly operates to output a current to the output terminal OUT and when the nMOS 26 mainly operates to input a current from the output terminal OUT, it is difficult to design a push-pull amplifier with a stable operation.
Moreover, for example, since the gain of the path on the n-channel transistor side becomes larger, the gain of the whole operational amplifier, using in its output stage the push-pull amplifier, becomes larger. Consequently, the capacitance value of the phase compensation capacitor 28 disadvantageously becomes larger. In a typical CMOS process, a gate insulator film is utilized to form a capacitor. For this reason, an increase in the capacitance value disadvantageously leads to an increase in the layout area of a push-pull amplifier and hence to an increase in the layout area of an operational amplifier using in its output stage the push-pull amplifier.
It is an object of the present invention to provide a push-pull amplifier with stable operation by reducing the difference between the gains at the respective push-pull transistors in the output stage of the push-pull amplifier with respect to the input signal.
In a form of the push-pull amplifier according to the present invention, a source follower circuit receives, at its gate, an input signal and outputs an input current that corresponds to the input signal. A current transfer circuit receives the input current and maintains constant the sum of the input current and an output current that is to be applied to a first node. A push-pull circuit includes a first transistor that directly receives, at its gate, the input signal and a second transistor having its gate connected to the first node. The push-pull circuit is responsive to the input signal to alternately activate the first and second transistors, thereby outputting output signals.
In this push-pull amplifier, the voltage gain of the source follower circuit that receives the input signal is equal to or less than 1. Thus, the gain of the gate voltage of the second transistor to the input signal can be reduced. Since the difference between the voltage gains at the first and second transistors can be reduced, it is possible to easily design a push-pull amplifier with a stable operation.
Moreover, in a case when the push-pull amplifier is used in the output stage of an operational amplifier, it is possible to reduce the gain of a circuit that transfers the output of the differential amplifier to the output stage. For this reason, the capacitance value of a phase compensation capacitor inserted between the input and output terminals can be reduced. As a result, the layout areas (chip areas) of the push-pull amplifier and operational amplifier can be reduced, resulting in a reduction in manufacturing cost. In addition, since the gain in the high frequency range increases, it is possible to provide amplification in a wider frequency band.
In another form of the push-pull amplifier according to the present invention, the current transfer circuit includes a first current mirror circuit, a second current mirror circuit and a constant-current source that supplies a constant current to a second node. The first current mirror circuit includes a first input transistor whose drain and gate are supplied with the input current, and a first output transistor that has its drain connected to the second node and that generates a first output current with the same value as the input current. The second current mirror circuit includes a second input transistor that has its drain and gate connected to the second node and that generates a second input current, and a second output transistor that has its drain connected to the first node and that supplies the first node with the output current with the same value as the second input current.
In the first current mirror circuit, the drain current flowing through the first input transistor (the input current) has the same value as the drain current flowing through the first output transistor (the first output current). In the second current mirror circuit, the drain current flowing through the second input transistor (the second input current) has the same value as the drain current flowing through the second output transistor (the second output current).
Both the drain of the first output transistor of the first current mirror circuit and the drain of the second input transistor of the second current mirror circuit are connected to the second node. For this reason, the sum of the first output current flowing through the first output transistor and the second input current flowing through the second input transistor is maintained at a constant value by the constant-current source. Therefore, as the first output current (=the input current) becomes greater, the second input current (=the second output current to be supplied to the first node) becomes smaller. Conversely, as the first output current (=the input current) becomes smaller, the second input current (=the second output current) becomes greater. In this way, merely connecting the two current mirror circuits in parallel can easily configure a current transfer circuit whose input and output currents sum into a constant value.
In yet another form of the push-pull amplifier,according to the present invention, a load transistor is disposed between the output of the source follower circuit and the input of the current transfer circuit and has its gate connected to a constant-voltage source. Since the gate of the load transistor is directly connected to the constant-voltage source, the gate-to-source voltage thereof is constant. The load transistor, therefore, always operates in the saturation region, and can prevent any deviation in the power supply voltage supplied to the source follower circuit from affecting the first current mirror circuit.